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Parameterized Counter

Intermediate

Simulate (Icarus Verilog)

00:00

Specification

01Operation

The counter has an enable and a synchronous reset.

Behavior

reset=1 clears count on the next rising edge.
enable=1 increments modulo 2^WIDTH; otherwise the value is retained.

02Interface

clk, reset, enable

Direction: Input
Width: 1 bit
Description: Clock and controls

count

Direction: Output
Width: WIDTH bits
Description: Counter value

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