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Leading-one Detector
Beginner
Simulate (Icarus Verilog)
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Import
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Specification
01
Operation
Locate the most-significant active bit.
Behavior
result
contains the index and
flag
indicates a nonzero word.
Boundary cases produce deterministic outputs.
The logic must remain purely combinational.
02
Interface
data_a
Direction
Input
Width
16 bits
Description
Primary data or state
data_b
Direction
Input
Width
16 bits
Description
Secondary data or context
control
Direction
Input
Width
4 bits
Description
Mode and controls
result
Direction
Output
Width
16 bits
Description
Main result
aux
Direction
Output
Width
8 bits
Description
Auxiliary result
flag
Direction
Output
Width
1 bit
Description
Decision or validity
leading_one_detector.v
Results
← One-hot Vector Analyzer