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8-bit Adder with Carry

Beginner

Simulate (Icarus Verilog)

00:00

Specification

01Operation

The full result is split into a sum and carry-out.

Behavior

{carry_out, sum} equals a + b + carry_in.
The calculation is unsigned and combinational.

02Interface

a, b

Direction: Input
Width: 8 bits
Description: Unsigned operands

carry_in

Direction: Input
Width: 1 bit
Description: Carry-in

sum

Direction: Output
Width: 8 bits
Description: Sum

carry_out

Direction: Output
Width: 1 bit
Description: Carry-out

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