>_FPGA Pour Tous Blog

Blog Careers Challenges Leaderboard Community Certification Projects The Club

Chargement…

>_FPGA Pour Tous

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Testbench
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

© 2026 FPGA Pour Tous

FAQ|Legal|Privacy|Terms

Asynchronous SRAM Controller

Advanced

Simulate (Icarus Verilog)

00:00

Specification

01Operation

The controller holds address, data, and strobes throughout all wait cycles.

Behavior

An accepted request is latched and raises busy.
Reads assert ce_n and oe_n low; writes assert ce_n and we_n low and data_oe high.
After WAIT_CYCLES, read data is captured and ready pulses for one cycle.

02Interface

clk, reset, request, write

Direction: Input
Width: 1 bit
Description: Clock and command

address, write_data

Direction: Input
Width: 16 bits
Description: Internal address and data

read_data, busy, ready

Direction: Output
Width: 16/1 bits
Description: Internal response

sram_address, sram_data_out

Direction: Output
Width: 16 bits
Description: Address and write data driven to SRAM

sram_data_in

Direction: Input
Width: 16 bits
Description: Read data received from SRAM

sram_ce_n, sram_oe_n, sram_we_n, sram_data_oe

Direction: Output
Width: 1 bit
Description: SRAM strobes

← 3 x 3 Sobel Operator