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MAC Unit

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

The block is synchronous: acc <= acc + a*b when i_valid=1.

Behaviour

Reset or i_clear clears the accumulator.
i_valid=1 adds the current product.
o_accum is 24 bits wide.

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high asynchronous reset

i_clear

Direction: Input
Width: 1 bit
Description: Internal clear

i_valid

Direction: Input
Width: 1 bit
Description: Valid input sample

i_a

Direction: Input
Width: 8 bits
Description: Input a

i_b

Direction: Input
Width: 8 bits
Description: Input b

o_accum

Direction: Output
Width: 24 bits
Description: Output accum

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