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Bitonic Sequence Detector

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

The circuit is combinational and requires one strict internal peak.

Behaviour

Valid if a0<a1>a2>a3 or a0<a1<a2>a3.
Plateaus are not accepted.
Fully increasing or decreasing sequences are rejected.

02Interface

i_a0

Direction: Input
Width: 4 bits
Description: Input a0

i_a1

Direction: Input
Width: 4 bits
Description: Input a1

i_a2

Direction: Input
Width: 4 bits
Description: Input a2

i_a3

Direction: Input
Width: 4 bits
Description: Input a3

o_is_bitonic

Direction: Output
Width: 1 bit
Description: Output is bitonic

← Mode Finder