4-Bit Carry Lookahead Adder

Intermediate

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Specification

01General Operation

4-bit Carry Lookahead (CLA) adder. All carries are computed in parallel from generate (g_i = a_i AND b_i) and propagate (p_i = a_i XOR b_i) signals, removing the Ripple-Carry serial chain.

Behaviour (pure combinational):

c1 = g_0 + p_0·c_in
c2 = g_1 + p_1·g_0 + p_1·p_0·c_in
c3 = g_2 + p_2·g_1 + p_2·p_1·g_0 + p_2·p_1·p_0·c_in
o_cout = g_3 + p_3·g_2 + ...
o_sum_i = p_i XOR c_i

*Latency = a single gate delay, independent of bit width.*

02Interface

i_a

Direction: Input
Width: 4 bits
Description: Operand A

i_b

Direction: Input
Width: 4 bits
Description: Operand B

i_cin

Direction: Input
Width: 1 bit
Description: Carry in

o_sum

Direction: Output
Width: 4 bits
Description: Sum

o_cout

Direction: Output
Width: 1 bit
Description: Carry out

← 4x8 Register File

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