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8x8 Dual-Port RAM

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

On rising edge, if i_we = '1', writes i_wdata at i_waddr. Read at i_raddr is asynchronous and independent from the write port.

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: Clock

i_we

Direction: Input
Width: 1 bit
Description: Write enable

i_waddr

Direction: Input
Width: 3 bits
Description: Write address

i_wdata

Direction: Input
Width: 8 bits
Description: Write data

i_raddr

Direction: Input
Width: 3 bits
Description: Read address

o_rdata

Direction: Output
Width: 8 bits
Description: Read data

← 8-Deep 8-Bit LIFO Stack