16x4 Synchronous RAM

Synchronous single-port 16×4 RAM (16 words of 4 bits). Wider variant of the 8×4 RAM, with a 4-bit address.

Behaviour:

• Write (i_we='1'): on the rising edge of i_clk, i_data is stored at address i_addr.
• Read (i_we='0'): o_data continuously reflects the cell pointed to by i_addr (asynchronous read).
• No hardware reset: power-on contents are undefined.

*Inferred as distributed RAM (LUTs) by synthesis tools.*