8x4 Synchronous RAM

Intermediate

00:00

Specification

01General Operation

On rising edge, if i_we = '1', data i_data is written at address i_addr. Output o_data continuously reflects the content at address i_addr (asynchronous read).

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: Clock

i_we

Direction: Input
Width: 1 bit
Description: Write enable

i_addr

Direction: Input
Width: 3 bits
Description: Address (0 to 7)

i_data

Direction: Input
Width: 4 bits
Description: Data to write

o_data

Direction: Output
Width: 4 bits
Description: Data read (asynchronous read)

← 16x4 ROM with Constant Array

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