1µs Tick Generator

Intermediate

00:00

Specification

01General Operation

The module generates a single-cycle pulse every microsecond. The system clock period is configurable via the g_MAIN_CLK_PER generic (in nanoseconds).

Reset is synchronous and active-high.

Generic g_MAIN_CLK_PER (default 10 ns for 100 MHz)
Synchronous active-high reset

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_rst

Direction: Input
Width: 1 bit
Description: Synchronous active-high reset

o_tick_1us

Direction: Output
Width: 1 bit
Description: 1-cycle pulse every 1µs

← W1C Register (Write-1-to-Clear)

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