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Fibonacci Generator

Beginner

Simulate (GHDL)

00:00

Specification

01General Operation

The output register holds the current term and advances on i_next.

Behaviour

Reset: o_value=0 and the next term is 1.
Each cycle with i_next=1 produces the next term.
Overflow wraps naturally on 8 bits.

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high asynchronous reset

i_next

Direction: Input
Width: 1 bit
Description: Input next

o_value

Direction: Output
Width: 8 bits
Description: Output value

← Thermometer to Binary Decoder