2-FF CDC Synchronizer with Edge Detection

Beginner

00:00

Specification

01General Operation

The CDC synchronizer transfers a signal between two independent clock domains using a two flip-flop chain. It outputs the synchronized signal along with single-cycle pulses detecting rising and falling edges.

Reset is asynchronous and active-high.

Edge detection must be combinational
Synchronizer flip-flops must have the ASYNC_REG attribute

02Interface

i_clk_dst

Direction: Input
Width: 1 bit
Description: Destination domain clock

i_reset_dst

Direction: Input
Width: 1 bit
Description: Active-high async reset

i_data_src

Direction: Input
Width: 1 bit
Description: Source domain signal

o_data_dst

Direction: Output
Width: 1 bit
Description: Synchronized signal

o_re_detected

Direction: Output
Width: 1 bit
Description: Rising edge pulse

o_fe_detected

Direction: Output
Width: 1 bit
Description: Falling edge pulse

← Generic Parallel Register with Enable

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