Generic Parallel Register with Enable

Beginner

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Specification

01General Operation

Parallel register of configurable width (g_width bits). Stores input data on the rising clock edge when enable is active. The o_updated output pulses for one cycle after each write.

Reset is asynchronous and active-high.

Generic g_width (default 8)

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high async reset

i_en

Direction: Input
Width: 1 bit
Description: Write enable

i_data

Direction: Input
Width: g_width bits
Description: Input data

o_q

Direction: Output
Width: g_width bits
Description: Register value

o_updated

Direction: Output
Width: 1 bit
Description: Update pulse

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