Loadable Shift Register

8-bit register combining parallel load and left shift. Loading copies the input data into the register. When i_shift is active, the register shifts left by one bit and inserts '0' at the LSB. Output o_msb continuously reflects the current MSB, o_reg(7); it does not store the bit that was just shifted out of the register. Load has priority over shift.

Reset is asynchronous and active-high.