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1D Convolution Engine

Advanced

Simulate (GHDL)

00:00

Specification

01General Operation

The module is sequential and keeps the two previous samples.

Behaviour

On each i_valid, compute x0 + 2*x1 + x2.
o_valid pulses with the computed output.
The output is 10-bit unsigned.

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high asynchronous reset

i_valid

Direction: Input
Width: 1 bit
Description: Valid input sample

i_sample

Direction: Input
Width: 8 bits
Description: Input sample

o_valid

Direction: Output
Width: 1 bit
Description: Valid output

o_sample

Direction: Output
Width: 10 bits
Description: Output sample

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