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The circuit is combinational. Master 0 has priority over master 1.
Behaviour
i_m0_req=1, the memory port receives master 0 signals.i_m1_req=1, it receives master 1 signals.i_mem_ready and i_mem_rdata are returned only to the granted master.i_m0_reqi_m0_wei_m0_addri_m0_wdatai_m1_reqi_m1_wei_m1_addri_m1_wdatai_mem_readyi_mem_rdatao_mem_valido_mem_weo_mem_addro_mem_wdatao_m0_readyo_m0_rdatao_m1_readyo_m1_rdata