AXI4-Lite Master

Advanced

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Specification

01General Operation

The module converts user requests (i_go, i_rnw, i_address, i_data_in) into AXI4-Lite transactions. For writes, AW, W, and B channels are managed. For reads, AR and R channels. The module signals transaction completion and read data.

Generics: G_AXI_DATA_WIDTH (default 32), G_AXI_ADDR_WIDTH (default 32)
Configurable strobe via G_AXI_STRB_PASSTHROUGH

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_rst

Direction: Input
Width: 1 bit
Description: Synchronous active-high reset

i_go

Direction: Input
Width: 1 bit
Description: Start transaction

i_rnw

Direction: Input
Width: 1 bit
Description: '1' = read, '0' = write

o_done

Direction: Output
Width: 1 bit
Description: Transaction done pulse

i_address

Direction: Input
Width: G_AXI_ADDR_WIDTH bits
Description: Target address

i_data_in

Direction: Input
Width: G_AXI_DATA_WIDTH bits
Description: Write data

i_wr_strb

Direction: Input
Width: G_AXI_DATA_WIDTH/8 bits
Description: Write strobe

o_data_out

Direction: Output
Width: G_AXI_DATA_WIDTH bits
Description: Read data

m00_axi_*

Direction: -
Width: -
Description: AXI4-Lite master signals (aw, w, b, ar, r)

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