Interrupt Generator

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Specification

01General Operation

The module manages a configurable number of interrupt vectors (g_NB_IT). When interrupts are enabled and a trigger is received, the corresponding vector produces a pulse of configurable minimum duration (g_MIN_WIDTH_PULSE cycles).

The module has no reset input. Registers are initialized to zero, and i_it_en='0' clears vectors, counters, and indicators on the following rising edge.

Generics g_NB_IT (default 4) and g_MIN_WIDTH_PULSE (default 4)

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_it_en

Direction: Input
Width: 1 bit
Description: Global IT enable

i_it_trig_valid

Direction: Input
Width: 1 bit
Description: Trigger vector valid

i_it_trig

Direction: Input
Width: g_NB_IT bits
Description: Trigger vector

o_it_activ_valid

Direction: Output
Width: 1 bit
Description: At least one counter finished

o_it_activ

Direction: Output
Width: g_NB_IT bits
Description: End-of-pulse vector

o_it_vect

Direction: Output
Width: g_NB_IT bits
Description: Active IT vector

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