>_
FPGA
Pour Tous
Blog
Blog
Careers
Challenges
Leaderboard
Community
Certification
Projects
The Club
FR
Chargement…
Windowed Watchdog Decision
Intermediate
Simulate (Icarus Verilog)
Templates
Full bundle
Joker
Sign in
00:00
Import
Report a bug
Specification
01
Operation
Classify a kick as early, valid, or late.
Behavior
result
encodes the three decisions as 1, 2, and 3.
Boundary cases produce deterministic outputs.
The logic must remain purely combinational.
02
Interface
data_a
Direction
Input
Width
16 bits
Description
Primary data or state
data_b
Direction
Input
Width
16 bits
Description
Secondary data or context
control
Direction
Input
Width
4 bits
Description
Mode and controls
result
Direction
Output
Width
16 bits
Description
Main result
aux
Direction
Output
Width
8 bits
Description
Auxiliary result
flag
Direction
Output
Width
1 bit
Description
Decision or validity
windowed_watchdog_decision.v
Results
← Reciprocal Frequency Estimator