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Switch Debouncer

Intermediate

Simulate (Icarus Verilog)

00:00

Specification

01Operation

A new value must remain stable for several cycles before being accepted.

Behavior

Two flip-flops synchronize noisy_in into the clk domain.
clean_out changes after STABLE_CYCLES consecutive equal samples that differ from its value.

02Interface

clk, reset

Direction: Input
Width: 1 bit
Description: Clock and synchronous reset

noisy_in

Direction: Input
Width: 1 bit
Description: Noisy asynchronous input

clean_out

Direction: Output
Width: 1 bit
Description: Filtered state

← Pulse Stretcher