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BCD Magnitude Comparator

Beginner

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Compare two BCD numbers after validation.

Behavior

result is FFFF, zero, or one according to the relation.
Boundary cases produce deterministic outputs.
The logic must remain purely combinational.

02Interface

data_a

Direction: Input
Width: 16 bits
Description: Primary data or state

data_b

Direction: Input
Width: 16 bits
Description: Secondary data or context

control

Direction: Input
Width: 4 bits
Description: Mode and controls

result

Direction: Output
Width: 16 bits
Description: Main result

aux

Direction: Output
Width: 8 bits
Description: Auxiliary result

flag

Direction: Output
Width: 1 bit
Description: Decision or validity

← Eight-bit Saturating Adder