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Ripple-carry Adder

Beginner

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Each intermediate carry feeds the next more-significant stage.

Behavior

Module full_adder computes one-bit sum and carry.
ripple_carry_adder chains four instances and exposes the final carry.

02Interface

a, b

Direction: Input
Width: 4 bits
Description: Operands

carry_in

Direction: Input
Width: 1 bit
Description: Initial carry

sum

Direction: Output
Width: 4 bits
Description: Sum

carry_out

Direction: Output
Width: 1 bit
Description: Final carry

← Serial-in Parallel-out Shift Register