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Chargement…
Cache Write-policy Unit
Advanced
Simulate (Icarus Verilog)
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Import
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Specification
01
Operation
Decide hit, allocation, or write-back.
Behavior
control
encodes valid, dirty, write, and allocation.
Boundary cases produce deterministic outputs.
The logic must remain purely combinational.
02
Interface
data_a
Direction
Input
Width
16 bits
Description
Primary data or state
data_b
Direction
Input
Width
16 bits
Description
Secondary data or context
control
Direction
Input
Width
4 bits
Description
Mode and controls
result
Direction
Output
Width
16 bits
Description
Main result
aux
Direction
Output
Width
8 bits
Description
Auxiliary result
flag
Direction
Output
Width
1 bit
Description
Decision or validity
cache_write_policy_unit.v
Results
← Urgent Memory Arbiter