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DRAM Refresh Decision Unit

Advanced

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Arbitrate between normal access and overdue refresh.

Behavior

control[0] indicates a busy bus.
Boundary cases produce deterministic outputs.
The logic must remain purely combinational.

02Interface

data_a

Direction: Input
Width: 16 bits
Description: Primary data or state

data_b

Direction: Input
Width: 16 bits
Description: Secondary data or context

control

Direction: Input
Width: 4 bits
Description: Mode and controls

result

Direction: Output
Width: 16 bits
Description: Main result

aux

Direction: Output
Width: 8 bits
Description: Auxiliary result

flag

Direction: Output
Width: 1 bit
Description: Decision or validity

← Digital PLL Loop Filter