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8N1 UART Transmitter

Advanced

Simulate (Icarus Verilog)

00:00

Specification

01Operation

Parameter CLKS_PER_BIT sets each bit duration.

Behavior

The idle line is high.
An accepted start sends 0, eight data bits LSB-first, then 1.
busy covers the complete frame and done pulses at completion.

02Interface

clk, reset, start

Direction: Input
Width: 1 bit
Description: Clock and controls

data_in

Direction: Input
Width: 8 bits
Description: Byte to transmit

tx

Direction: Output
Width: 1 bit
Description: Serial output

busy, done

Direction: Output
Width: 1 bit
Description: Transmission status

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