Testbench

Verify ordering, empty/full flags and simultaneous operations.

FIFO EmptyFIFO Full

Testbench: Single-port RAM 256x8

Verify synchronous writes and reads at several addresses.

AddressRead

Testbench: Dual-port RAM 128x16

Verify writes on port A and independent reads on port B.

AddressRead

Testbench: Interrupt generator

Verify pulse width and interrupt-vector capture in the status register.

Pulse Width

Testbench: UART transmitter

Verify start, data and stop bits together with the busy signal.

Start BitData Bits

Testbench: Tick-driven stopwatch timer

VHDL

Verify reset, loading, countdown and the completion pulse.

Complete Testbench: UART transmitter

Testbench: Memory arbiter

VHDL

Verify rotating priority, one-hot grants and respect for backpressure.

Complete Testbench: Tick-driven stopwatch timer

Testbench: Signed multiplier

VHDL

Verify signed products, zero and representable boundaries.

Complete Testbench: Memory arbiter

Testbench: Modulo-m adder-subtractor

VHDL

Verify sum and difference reduction within the modulo interval.

Complete Testbench: Signed multiplier

Testbench: Nonrestoring divider

VHDL

Verify quotient, remainder and explicit division-by-zero behavior.