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Exercises
31
Done
0
Total
31
TOP_LEVEL - BCD 7-Segment Counter
Wire the provided components into a structural TOP_LEVEL.
N-bit Comparator
Implement a parametric comparator capable of comparing two unsigned values.
Double Flip-Flop Synchronizer
Implement a two-stage synchronizer to safely transfer an asynchronous signal into a clock domain.
Rising Edge Detector
Implement a rising edge detector that generates a one-clock-cycle pulse on each 0→1 transition of the input signal.
Falling Edge Detector
Implement a falling edge detector that generates a one-clock-cycle pulse on each 1→0 transition of the input signal.
4:1 Mux from 2:1 Muxes
Build a 4-to-1 multiplexer by instantiating three 2-to-1 multiplexers from the package.
2-to-4 Decoder
Implement a 2-to-4 binary decoder with active-high one-hot output.
4-to-2 Priority Encoder
Implement a 4-to-2 priority encoder: the binary output gives the index of the highest active bit in `i_d`.
Half Subtractor
Implement a 1-bit half subtractor producing the difference and the outgoing borrow.
8-bit Parity Detector (XOR Tree)
Compute the even parity of an 8-bit word using a 3-level XOR tree.
4-bit Ripple-Carry Adder
Build a 4-bit adder by chaining four 1-bit full-adders provided in the package.
D Flip-flop with Async Set/Reset
Implement a D flip-flop with asynchronous set and reset, both priority over the clock.
T Flip-flop from D Flip-flop
Build a T flip-flop by wiring a D flip-flop with an XOR gate.
3-bit Asynchronous (Ripple) Counter
Build a 3-bit ripple counter by chaining three T flip-flops from the package.
Divide-by-4 Frequency Divider
Cascade two T flip-flops to produce a clock four times slower than `i_clk`.
Serial-to-Parallel Converter
Code a parameterized shift register using a `generate` structure.
CRC-8 Generator
Implement a CRC-8 generator (polynomial 0x07: x⁸+x²+x+1) processing one bit per clock cycle.
Vending Machine (Moore FSM)
Implement the FSM of a vending machine accepting 3 tokens then dispensing a drink on button press.
4-digit Code Lock (Moore FSM)
Implement an FSM that unlocks if sequence `1, 2, 3, 4` is entered correctly.
3-floor Elevator (Moore FSM)
Implement the FSM of a 3-floor elevator moving toward the target floor.
Round-Robin Arbiter 2 masters (FSM)
Implement a round-robin arbiter between two masters: priority swaps after each grant.
4-phase Handshake Master (FSM)
Implement the master FSM of a 4-phase handshake protocol (req/ack).
Automatic Door with Safety (FSM)
Implement the FSM of an automatic door with obstacle sensor and end-of-travel sensors.
Sequence Detector "1101" (Moore vs Mealy)
Implement the same sequence detector in two flavours: Moore and Mealy machines.
4x4 Matrix Keypad (Scan FSM)
Implement the sequential scan of a 4x4 matrix keypad and identify the pressed key.
Tree Reduced XOR
Describe a parameterized reduced XOR as a tree for a power-of-two width.
mu0 - Top-level assembly
Wire the mu0 processor components to build a functional top level.
UART - Top-level assembly
Wire the top-level of a full UART (TX + RX) from the provided components.
Repeated-Addition Multiplier
Rebuild an FSMD that multiplies two 8-bit operands using repeated additions.
GCD by Subtractions
Recode a GCD FSMD based on comparisons, swap and subtraction.
Square-Root Approximation
Rebuild an FSMD that approximates the magnitude of two signed 8-bit values.