Chargement…
Chargement…
Reuse an 18-bit carry-save stage to absorb one operand per cycle. Keep the sum and carry bits separate so that carry does not propagate during compression. After the fourth operand, perform one carry-propagating addition to produce the result.
Latch all four inputs on i_start while idle. Keep o_busy='1' through the four compression cycles, then pulse o_done for one cycle. Synchronous active-high reset clears all state.
The testbench checks different bit patterns, zero, the maximum sum, and the completion pulse.