>_FPGA Pour Tous Blog

Blog Careers Challenges Leaderboard Community Certification Projects The Club

Chargement…

>_FPGA Pour Tous

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Testbench
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

© 2026 FPGA Pour Tous

FAQ|Legal|Privacy|Terms

Digital Differentiator

Intermediate

Simulate (GHDL)

00:00

Specification

01General Operation

The module stores the last valid sample and outputs a signed delta.

Behaviour

The first valid sample initializes memory and produces no delta.
Following samples produce i_sample - previous on o_diff.
o_valid pulses when the delta is available.

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high asynchronous reset

i_valid

Direction: Input
Width: 1 bit
Description: Valid input sample

i_sample

Direction: Input
Width: 8 bits
Description: Input sample

o_diff

Direction: Output
Width: 9 bits
Description: Output diff

o_valid

Direction: Output
Width: 1 bit
Description: Valid output

← Leading Zero Counter