4-Bit PISO Register

On reset, the register and internal counter are cleared. When i_load='1', i_parallel is loaded and o_valid indicates that a 4-bit sequence is available. When i_shift='1', the current bit is sent on o_serial, then the register shifts to the next bit.

Behaviour

• MSB first serial output;
• i_load has priority over i_shift;
• o_valid='1' while at least one bit remains to transmit;
• synchronous active-high reset.