>_FPGA Pour Tous Blog

Blog Careers Challenges Leaderboard Community Certification Projects The Club

Chargement…

>_FPGA Pour Tous

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Testbench
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

© 2026 FPGA Pour Tous

FAQ|Legal|Privacy|Terms

Prefix Sum

Beginner

Simulate (GHDL)

00:00

Specification

01General Operation

The circuit is combinational and produces all four prefixes in parallel.

Behaviour

o_p0 = i_a0.
o_p1 = i_a0 + i_a1.
o_p2 and o_p3 continue the same accumulation.

02Interface

i_a0

Direction: Input
Width: 4 bits
Description: Input a0

i_a1

Direction: Input
Width: 4 bits
Description: Input a1

i_a2

Direction: Input
Width: 4 bits
Description: Input a2

i_a3

Direction: Input
Width: 4 bits
Description: Input a3

o_p0

Direction: Output
Width: 6 bits
Description: Output p0

o_p1

Direction: Output
Width: 6 bits
Description: Output p1

o_p2

Direction: Output
Width: 6 bits
Description: Output p2

o_p3

Direction: Output
Width: 6 bits
Description: Output p3

← Stream Accumulator