PWM Generator

Beginner

00:00

Specification

01General Operation

The PWM generator produces a periodic signal whose duty cycle is controlled by i_duty. The signal period is set by the g_clk_hz and g_pwm_hz generics. The output is active when the internal counter is below the duty value.

Reset is asynchronous and active-high.

Generics g_clk_hz (default 100,000,000) and g_pwm_hz (default 1,000)

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high async reset

i_duty

Direction: Input
Width: 16 bits (unsigned)
Description: Duty cycle

o_pwm

Direction: Output
Width: 1 bit
Description: PWM signal

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