>_FPGA Pour Tous Blog

Blog Careers Challenges Leaderboard Community Certification Projects The Club

Chargement…

>_FPGA Pour Tous

Learn VHDL, from beginner to expert.

Courses

VHDL
Verilog
SystemVerilog
FPGA
Hardware and PCB
Digital Electronics
Protocols
Zynq

Practice

All exercises
HW to simulation
VHDL specifications
Verilog specifications
Software to schematic
Block Design
Testbench
Leaderboard
Report a bug

Blog

FPGA & VHDL articles
Challenges
Certification
Community
FAQ

© 2026 FPGA Pour Tous

FAQ|Legal|Privacy|Terms

Merge Sorted Streams

Advanced

Simulate (GHDL)

00:00

Specification

01General Operation

The circuit is combinational and keeps duplicates.

Behaviour

i_a0<=i_a1 and i_b0<=i_b1 are assumed true.
o_s0..o_s3 form the ascending merge.
Values are unsigned 4-bit numbers.

02Interface

i_a0

Direction: Input
Width: 4 bits
Description: Input a0

i_a1

Direction: Input
Width: 4 bits
Description: Input a1

i_b0

Direction: Input
Width: 4 bits
Description: Input b0

i_b1

Direction: Input
Width: 4 bits
Description: Input b1

o_s0

Direction: Output
Width: 4 bits
Description: Output s0

o_s1

Direction: Output
Width: 4 bits
Description: Output s1

o_s2

Direction: Output
Width: 4 bits
Description: Output s2

o_s3

Direction: Output
Width: 4 bits
Description: Output s3

← Bubble Sort Engine