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IIR Biquad Filter

Advanced

Simulate (GHDL)

00:00

Specification

01General Operation

The filter keeps two input samples and two previous outputs.

Behaviour

Formula: y = x + x1 + x2 - y1/2 + y2/4.
8-bit signed input, 16-bit signed output.
o_valid pulses for each valid input.

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_reset

Direction: Input
Width: 1 bit
Description: Active-high asynchronous reset

i_valid

Direction: Input
Width: 1 bit
Description: Valid input sample

i_sample

Direction: Input
Width: 8 bits
Description: Input sample

o_valid

Direction: Output
Width: 1 bit
Description: Valid output

o_sample

Direction: Output
Width: 16 bits
Description: Output sample

← Asynchronous FIFO