AXI4 Master - Write Channels

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Specification

01General Operation

AXI4 single-beat write master. A one-cycle i_write_go='1' pulse triggers a transaction. The three channels AW (address), W (data), and B (response) operate independently with VALID/READY handshake. WLAST='1' always (single-beat).

02Interface

i_clk

Direction: Input
Width: 1 bit
Description: System clock

i_rst

Direction: Input
Width: 1 bit
Description: Synchronous reset

i_write_go

Direction: Input
Width: 1 bit
Description: Write trigger

i_wr_addr

Direction: Input
Width: 32 bits
Description: Write address

i_wdata

Direction: Input
Width: 32 bits
Description: Write data

o_wr_done

Direction: Output
Width: 1 bit
Description: Write done pulse (1 cycle)

m_axi_awaddr

Direction: Output
Width: 32 bits
Description: AXI Write Address

m_axi_awvalid

Direction: Output
Width: 1 bit
Description: AXI AW Valid

m_axi_awready

Direction: Input
Width: 1 bit
Description: AXI AW Ready

m_axi_wdata

Direction: Output
Width: 32 bits
Description: AXI Write Data

m_axi_wstrb

Direction: Output
Width: 4 bits
Description: AXI Write Strobe

m_axi_wlast

Direction: Output
Width: 1 bit
Description: AXI Write Last

m_axi_wvalid

Direction: Output
Width: 1 bit
Description: AXI W Valid

m_axi_wready

Direction: Input
Width: 1 bit
Description: AXI W Ready

m_axi_bresp

Direction: Input
Width: 2 bits
Description: AXI Write Response

m_axi_bvalid

Direction: Input
Width: 1 bit
Description: AXI B Valid

m_axi_bready

Direction: Output
Width: 1 bit
Description: AXI B Ready

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